Broadway is the codename of the 32-bit central processing unit (CPU) used in Nintendo's Wii home video game console. It was designed by IBM, and was initially produced using a 90 nm SOI process and later produced with a 65 nm SOI process.
 | |
| General information | |
|---|---|
| Launched | 2006 |
| Discontinued | October 22nd, 2013 |
| Designed by | IBM and Nintendo |
| Common manufacturer | |
| Performance | |
| Max. CPU clock rate | 729 MHz |
| Cache | |
| L1 cache | 32/32 kB |
| L2 cache | 256 kB |
| Architecture and classification | |
| Application | Wii |
| Technology node | 90 nm (2006–2007), 65 nm (2007–2013) |
| Microarchitecture | PowerPC G3 |
| Instruction set | PowerPC (PowerPC ISA 1.10) |
| Physical specifications | |
| Cores |
|
| GPU | Hollywood |
| Products, models, variants | |
| Variant | |
| History | |
| Predecessor | Gekko |
| Successor | Espresso |
According to IBM, the processor consumes 20% less power than its predecessor, the 180 nm Gekko used in the GameCube video game console.[1]
Broadway was produced by IBM at their semiconductor development and manufacturing facility in East Fishkill, New York (now owned by GlobalFoundries). The bond, assembly, and test operation for the Broadway module was performed at the IBM facility in Bromont, Quebec. Very few official details have been released to the public by Nintendo or IBM; unofficial reports claim it is derived from the 486 MHz Gekko architecture used in the GameCube and runs 50% faster at 729 MHz.[2]
The PowerPC 750CL, released in 2006, is a stock CPU offered by IBM; it is virtually identical to Broadway, but was provided in multiple clock speed variants (ranging from 400 MHz–1000 MHz.)[3][4][5]
Specifications
edit- 90 nanometer process technology, shrunk to 65 nm in 2007. [6]
- Superscalar Out-of-order execution PowerPC core, specially modified for the Wii platform
- IBM silicon on insulator (SOI) technology
- Backward compatible with the Gekko processor
- 729 MHz
- 4 stages long Two integer ALUs (IU1 and IU2) – 32 bit
- 7 stages long 64-bit floating-point unit (FPU) (or 2 × 32-bit SIMD, often found under the denomination "paired singles")
- Branch Prediction Unit (BPU)
- Load-Store Unit (LSU)
- System Register Unit (SRU)
- Memory Management Unit (MMU)
- Branch Target Instruction Cache (BTIC)
- SIMD Instructions – PowerPC750 + Roughly 50 new SIMD instructions, geared toward 3D graphics
- 64 kB L1 cache (32 kB instruction + 32 kB data)
- 256 kB L2 cache
- 2.9 GFLOPS
External bus
edit- 64-bit
- 243 MHz
- 1.944 gigabytes per second bandwidth
Gallery
edit
39X6735, 2006
90 nm, 21×21 mm package
43E4048, 2006-2007
90 nm, 21×21 mm package
43E5070, 2007-2008
65 nm, 21×21 mm package
48J2662, 2008-2016
65 nm, 15×15 mm package
References
edit- ^ IBM (2006). "IBM Ships First Microchips for Nintendo's Wii Video Game System". Archived from the original on October 11, 2006. Retrieved 2006-09-08.
- ^ "Wii Technical Specification, Wii". Archived from the original on 2011-08-10. Retrieved 2009-05-29.
- ^ "IBM Broadway RISC Microprocessor User's Manual, v0.6" (PDF). p. 61. Archived from the original (PDF) on 2013-12-04.
- ^ "IBM PowerPC 750CL Microprocessor Revision Level DD2.x" (PDF). Archived from the original (PDF) on 2013-06-03.
- ^ "IBM PowerPC 750CL RISC Microprocessor User's Manual" (PDF). Archived from the original (PDF) on 2012-11-15.
- ^ "Wii U CPU |Espresso| die Photo - Courtesy of Chipworks".