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Memory refresh

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Memory refresh is a process of periodically reading information from an area of computer memory and immediately rewriting the read information to the same area without modification, for the purpose of preserving the information.[1] Memory refresh is a background maintenance process required during the operation of semiconductor dynamic random-access memory (DRAM), the most widely used type of computer memory, and in fact is the defining characteristic of this class of memory.[2]

In a DRAM chip, each bit of memory data is stored as the presence or absence of an electric charge on a small capacitor on the chip.[2][3] As time passes, the charges in the memory cells leak away, so without being refreshed the stored data would eventually be lost. To prevent this, external circuitry periodically reads each cell and rewrites it, restoring the charge on the capacitor to its original level. Each memory refresh cycle refreshes a succeeding area of memory cells, thus repeatedly refreshing all the cells on the chip in a consecutive cycle. This process is typically conducted automatically in the background by the memory circuitry and is transparent to the user.[2] While a refresh cycle is occurring the memory is not available for normal read and write operations, but in modern memory this overhead is not large enough to significantly slow down memory operation.

Static random-access memory (SRAM) is electronic memory that does not require refreshing.[2] An SRAM memory cell requires four to six transistors, compared to a single transistor and a capacitor for DRAM; therefore, SRAM circuits require more area on a chip. As a result, data density is much lower in SRAM chips than in DRAM, and gives SRAM a higher price per bit. Therefore, DRAM is used for the main memory in computers, video game consoles, graphics cards and applications requiring large capacities and low cost.[4] The need for memory refresh makes DRAM more complicated, but the density and cost advantages of DRAM justify this complexity.

Operation

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While the memory is operating, each memory cell must be refreshed repetitively and within the maximum interval between refreshes specified by the manufacturer, usually in the millisecond region. Refreshing does not employ the normal memory operations (read and write cycles) used to access data, but specialized cycles called refresh cycles which are generated by separate counter circuits and interspersed between normal memory accesses.[5][6]

The storage cells on a memory chip are laid out in a rectangular array of rows and columns. The read process in DRAM is destructive and removes the charge on the memory cells in an entire row, so there is a column of specialized latches on the chip called sense amplifiers, one for each column of memory cells, to temporarily hold the data. During a normal read operation, the sense amplifiers after reading and latching the data, rewrite the data in the accessed row.[2][7] This arrangement allows the normal read electronics on the chip to refresh an entire row of memory in parallel, significantly speeding up the refresh process. Although a normal read or write cycle refreshes a row of memory, normal memory accesses cannot be relied on to hit all the rows within the necessary time, necessitating a separate refresh process. Rather than use the normal read cycle in the refresh process, to save time, an abbreviated refresh cycle is used. The refresh cycle is similar to the read cycle, but executes faster for two reasons:

  • For a refresh, only the row address is needed, so a column address doesn't have to be applied to the chip address circuits.
  • Data read from the cells does not need to be fed into the output buffers or the data bus to send to the CPU.

To ensure that each cell gets refreshed within the refresh time interval, the refresh circuitry must perform a refresh cycle on each of the rows on the chip within the interval.

Types of refresh circuits

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Although in some early systems the microprocessor controlled refresh, with a timer triggering a periodic interrupt that ran a subroutine that performed the refresh, this meant the microprocessor could not be paused, single-stepped, or put into energy-saving hibernation without stopping the refresh process and losing the data in memory.[6] So in modern systems refresh is handled by circuits in the memory controller,[2] which may be embedded in the chip itself. Specialized DRAM chips, such as pseudostatic RAM (PSRAM), have all the refresh circuitry on the chip, and function like static RAM as far as the rest of the computer is concerned.[8]

Usually the refresh circuitry consists of a refresh counter which contains the address of the row to be refreshed which is applied to the chip's row address lines, and a timer that increments the counter to step through the rows.[5] This counter may be part of the memory controller circuitry or on the memory chip itself. Two scheduling strategies have been used:[6]

  • Burst refresh – a series of refresh cycles are performed one after another until all the rows have been refreshed, after which normal memory accesses occur until the next refresh is required
  • Distributed refresh – refresh cycles are performed at regular intervals, interspersed with memory accesses.

Burst refresh results in long periods when the memory is unavailable, so distributed refresh has been used in most modern systems,[5] particularly in real-time systems. In distributed refresh, the interval between refresh cycles is

 

For example, DDR SDRAM has a refresh time of 64 ms and 8,192 rows, so the refresh cycle interval is 7.8 μs.[5][9]

Generations of DRAM chips developed after 2012 contain an integral refresh counter, and the memory control circuitry can either use this counter or provide a row address from an external counter. These chips have three standard ways to provide refresh, selected by different patterns of signals on the column select (CAS) and row select (RAS) lines:[6]

  • RAS only refresh – In this mode the address of the row to refresh is provided by the address bus lines typically generated by external counters in the memory controller.
  • CAS before RAS refresh (CBR) – In this mode the on-chip counter keeps track of the row to be refreshed and the external circuit merely initiates the refresh cycles.[5] This mode uses less power because the memory address bus buffers don't have to be powered up. It is used in most modern computers.
  • Hidden refresh – This is an alternate version of the CBR refresh cycle which can be combined with a preceding read or write cycle.[5] The refresh is done in parallel during the data transfer, saving time.

Since the 2012 generation of DRAM chips, the RAS only mode has been eliminated, and the internal counter is used to generate refresh. The chip has an additional sleep mode, for use when the computer is in sleep mode, in which an on-chip oscillator generates internal refresh cycles so that the external clock can be shut down.

Refresh overhead

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The fraction of time the memory spends on refresh, the refresh overhead, can be calculated from the system timing:[10]

 

For example, an SDRAM chip has 213=8,192 rows, a refresh interval of 64 ms, the memory bus runs at 133 MHz, and the refresh cycle takes 4 clock cycles.[10] The time for a refresh cycle is[10]

 
 
 

So less than 0.4% of the memory chip's time will be taken by refresh cycles. In SDRAM chips, the memory in each chip is divided into banks which are refreshed in parallel, saving further time. So the number of refresh cycles needed is the number of rows in a single bank, given in the specifications, which in the 2012 generation of chips has been frozen at 8,192.[needs update]

Refresh interval

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The maximum time interval between refresh operations is standardized by JEDEC for each DRAM technology and is specified in the manufacturer's chip specifications. It is usually in the range of milliseconds for DRAM and microseconds for eDRAM. For DDR2 SDRAM chips it is 64 ms.[11]: 20  Maximum refresh interval depends on the ratio of charge stored in the memory cell capacitors to leakage currents. Because the leakage currents in semiconductors increase with temperature, refresh intervals must be decreased at high temperatures. DDR2 SDRAM chips have a temperature-compensated refresh structure; refresh interval must be halved when chip case temperature exceeds 85 °C (185 °F).[11]: 49  Although the geometry of the capacitors has been shrinking with each new generation of memory chips, reducing the charge stored, refresh intervals for DRAM have been increasing; from 8 ms for 1M chips, 32 ms for 16M chips, to 64 ms for 256M chips. Longer refresh interval means a smaller fraction of the device's time is occupied with refresh, leaving more time for memory accesses. This improvement is achieved mainly by reduced leakage.

The actual persistence of readable charge values and thus data in most DRAM memory cells is much longer than the refresh interval, up to 1–10 seconds.[12] However, transistor leakage currents vary widely between different memory cells on the same chip due to process variation. In order to make sure that all the memory cells are refreshed before a single bit is lost, manufacturers must set their refresh times conservatively short.[13]

This frequent DRAM refresh consumes a third of the total power drawn by low-power electronics devices in standby mode. Researchers have proposed several approaches for extending battery run-time between charges by reducing the refresh rate, including temperature-compensated refresh (TCR) and retention-aware placement in DRAM (RAPID). Experiments show that in a typical off-the-shelf DRAM chip, only a few weak cells really require the worst-case 64 ms refresh interval,[14] and even then only at the high end of its specified temperature range. At room temperature (e.g. 24 °C (75 °F)), those same weak cells need to be refreshed once every 500 ms for correct operation. If the system can avoid using the weakest 1% of pages, a typical DRAM only needs to be refreshed once a second, even at 70 °C (158 °F), for correct operation of the remaining 99% of the pages. Some experiments combine these two complementary techniques, giving correct operation at room temperature at refresh intervals of 10 seconds.[14]

For error-tolerant applications (e.g. graphics applications), refreshing non-critical data stored in DRAM or eDRAM at a rate lower than their retention period saves energy with minor quality loss, which is an example of approximate computing.[15][16]

SRAM and DRAM memory technologies

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SRAM

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In static random-access memory (SRAM), another type of semiconductor memory, the data is not stored as charge on a capacitor, but in a bistable circuit, so SRAM does not need to be refreshed. The two basic types of memory have advantages and disadvantages. Static memory can be considered permanent while powered on, i.e., once written the memory stays until specifically changed and thus, its use tends to be simple in terms of system design. However, the internal construction of each SRAM cell requires six transistors, compared to the single transistor required for a DRAM cell, so the density of SRAM is much lower and price-per-bit much higher than DRAM.

CPU-based refresh

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Some early microprocessors (e.g. the Zilog Z80) provided special internal registers that could provide the Row Address Strobe (RAS) to refresh dynamic memory cells, the register being incremented on each refresh cycle. This could also be accomplished by other integrated circuits already being used in the system, if these already generated cycling accesses across RAM (e.g. the Motorola 6845). In CPUs such as the Z80, the availability of a RAS refresh was a big selling point due to its simplifying hardware design. Here, RAS refresh is signaled by a unique combination of address and control wires during operationally redundant clock cycles (T-States), i.e. during instruction decode and execution when the buses may not be required. Instead of the bus being inactive during such T-states, the refresh register would be presented on the address bus along with a combination of control signals to activate the refresh circuitry.

In early versions of the Z80, the ubiquity of 16 kB RAM chips having 128 rows and something of a lack of foresight resulted in the R register only incrementing over a 7 bit-wide range (0–127, 128 rows); the 8th bit could be set by the user, but would be left unchanged by the internal cycling. With the advent of 64 kbit+ DRAM chips (with 256 rows), extra circuitry or logic had to be built around the refresh signal to synthesize the missing 8th bit and prevent blocks of memory contents from being lost after a few milliseconds. In some contexts, it was possible to utilize interrupts and software to flip the 8th bit at the appropriate time and thus cover the entire range of the R register (256 rows). Another method, perhaps more universal but also more complex in terms of hardware, was to use an 8-bit counter chip, whose output would provide the refresh RAS address instead of the R register. The refresh signal from the CPU was used as the clock for this counter, resulting in the memory row being incremented with each refresh cycle. Later versions and licensed work-alikes of the Z80 core remedied the non-inclusion of the 8th bit in automatic cycling, and modern CPUs have greatly expanded on such basic provisioning to provide rich all-in-one solutions for DRAM refresh.

Pseudostatic DRAM

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Pseudostatic RAM (PSRAM or PSDRAM) is dynamic RAM with built-in refresh and address-control circuitry to make it behave similarly to SRAM. It combines the high density of DRAM with the ease of use of true SRAM. PSRAM (made by Numonyx) is used in the Apple iPhone and other embedded systems.[17]

Some DRAM components have a self-refresh standby mode. It is provided primarily to allow a system to suspend operation of its DRAM controller to save power without losing data stored in DRAM, whereas PSRAM allows operation without a separate DRAM controller. An embedded variant of PSRAM is sold by MoSys under the name 1T-SRAM. It is technically DRAM, but behaves much like SRAM, and is used in the GameCube and Wii consoles.

Other memory technologies using refresh

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Several early computer memory technologies also required periodical processes similar in purpose to the memory refreshing. The Williams tube has the closest similarity, since, as with DRAM, it is essentially a capacitive memory in which the values stored for each bit would gradually decay unless refreshed.

In magnetic-core memory, each memory cell can retain data indefinitely even with the power turned off, but reading the data from any memory cell erases its contents. As a consequence, the memory controller typically added a refresh cycle after each read cycle in order to create the illusion of a non-destructive read operation. Some early computers implemented atomic read–modify–write cycles (combined read and write with modify) for increment and decrement.

Delay-line memory requires constant refreshing because the data is actually stored as a signal in a transmission line. In this case, the refresh rate is comparable to the memory access time.

See also

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References

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  1. ^ "refresh cycle" in Laplante, Phillip A. (1999). Comprehensive Dictionary of Electrical Engineering. Springer. p. 540. ISBN 3540648356.
  2. ^ a b c d e f Ganssle, Jack; Tammy Noergaard; Fred Eady; Lewin Edwards; David J. Katz (2007). Embedded Hardware. Newnes. p. 106. ISBN 978-0750685849.
  3. ^ Jacob, Bruce; Spencer Ng; David Wang (2007). Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann. pp. 431–432. ISBN 978-0123797513.
  4. ^ Laasby, Gitte (March 10, 2014). "Consumers eligible for money under computer chip price-fixing settlement". Milwaukee Journal-Sentinel. Milwaukee, Wisconsin. Retrieved April 16, 2024.
  5. ^ a b c d e f Reinhardt, Steven K. (1999). "Memory, p. 9–3" (PDF). EECS 373 Design of Microprocessor-based Systems, Lecture Notes, Fall 1999. Electrical Engineering Dept., Univ. of Michigan. Archived (PDF) from the original on January 2, 2014. Retrieved April 16, 2024.
  6. ^ a b c d Heath, Steve (2003). Embedded Systems Design, 2nd Ed. Newnes. pp. 88–89. ISBN 0750655461.
  7. ^ "Memory 1997" (PDF). Integrated Circuit Engineering. 1997. p. 7.4. on The Chip Collection, Smithsonian website
  8. ^ Kumar (2009). Fundamentals of Digital Circuits, 2nd Ed. India: PHI Learning Pvt. Ltd. p. 819. ISBN 978-8120336797.
  9. ^ "JEDEC Double Data Rate (DDR) SDRAM Specification" (PDF). JESD79C. JEDEC Solid State Technology Assoc. March 2003. Retrieved April 16, 2024., p.20, on School of Engineering and Computer Science, Baylor Univ. website
  10. ^ a b c Godse, Deepali A.; Godse, Atul P. (2008). Computer Organization. India: Technical Publications. p. 4.23. ISBN 978-8184313567.
  11. ^ a b "JEDEC DDR2 SDRAM Specification" (PDF). ECS.Baylor.edu. JESD79-2b. JEDEC Solid State Technology Assoc. January 2005. Retrieved April 16, 2024.
  12. ^ Jacob, 2007, p.356
  13. ^ Bhati, Ishwar; Chang, Mu-Tien; Chishti, Zeshan; Lu, Shih-Lien; Jacob, Bruce (2016). "DRAM Refresh Mechanisms, Penalties, and Trade-Offs". IEEE Transactions on Computers. 65 (1): 108–121. doi:10.1109/TC.2015.2417540.
  14. ^ a b Ravi K. Venkatesan, Stephen Herr, Eric Rotenberg. "Retention-Aware Placement in DRAM (RAPID): Software Methods for Quasi-Non-Volatile DRAM". 2006.
  15. ^ Raha, A.; Sutar, S.; Jayakumar, H.; Raghunathan, V. (July 2017). "Quality Configurable Approximate DRAM". IEEE Transactions on Computers. 66 (7): 1172–1187. doi:10.1109/TC.2016.2640296. ISSN 0018-9340.
  16. ^ Kim, Yongjune; Choi, Won Ho; Guyot, Cyril; Cassuto, Yuval (December 2019). "On the Optimal Refresh Power Allocation for Energy-Efficient Memories". 2019 IEEE Global Communications Conference (GLOBECOM). Waikoloa, HI, USA: IEEE. pp. 1–6. arXiv:1907.01112. doi:10.1109/GLOBECOM38437.2019.9013465. ISBN 978-1-7281-0962-6. S2CID 195776538.
  17. ^ EE Times teardown of iPhone 3G
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