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Error re ALUs
editThe PC/3270 imformation states that its main processor was a 68000 with microprogram changed to execute IBM360 code. It states that the 68000 hardware is 3 16bit ALUs with multiple 16-bit register files. 2 ALUs and 2 reg files are joined as the "32-bit" data unit and 1 ALU and 16bit reg file is for address calculation. (Most address offset instructions are 16bit offsets.). Internal data buses are 16-bit which more precisely indicates CPU class. Its design and introduction was in the PDP11 and 8086 16-bit era. Should note the limitations of the original 64-pin DIP version versus PGA and flatpack versions (extra address and control pins). TaylorLeem (talk) 20:55, 23 May 2021 (UTC)
- Presumably by "PC/3270" you mean "XT/370" (the IBM 3270 was a line of terminals, and there were IBM PC models with communication hardware and terminal emulation software to emulate a 3270, which is what a "PC/3270" would be). The article just says:
A modified version of the 68000 formed the basis of the IBM XT/370 hardware emulator of the System 370 processor.
- Is there some issue with that particular claim? Or is the issue with the description of the 68000 hardware in general?
- What the article states about the 68000 hardware is
The design implements a 32-bit instruction set, with 32-bit registers and a 16-bit internal data bus. ... Internally, it uses a 16-bit data arithmetic logic unit (ALU) and two more 16-bit ALUs used mostly for addresses,
- so it states that the hardware is 3 16-bit ALUs with 32-bit registers, which is the case, other than the two "16-bit ALUs used mostly for addresses" being just AUs, not capable of doing logical (bitwise) operations.
- A Byte Magazine article by somebody from Motorola says that
The MC68000 has a 16-bit-wide ALU that essentially performs all data calculations and provides single-pass evaluation of the 16-bit data, for which the MC68000 is primarily designed. There are also two other internal arithmetic units. Both are 16 bits wide and are generally used in conjunction with each other to perform the various address calculations associated with operand effective addresses. This makes sense because all addresses are 32 bits wide.
- so, no, there isn't "1 ALU and 16bit reg file ... for address calculation". The A registers are 32-bit, just like the D registers, so if they're implemented with two 16-bit halves (so that the two halves can be separately run through 16-bit ALUs/AUs and data paths), two halves are joined to make data registers and two halves are joined to make arithmetic registers. Furthermore, there is only one ALU for data operations, and there are two AUs for address operations; address offsets might be mostly 16-bit, but addresses are 32-bit until they get chopped to 24 bits when they leave the chip.
- Were there any PGA or flatpack versions of the 68000? There was a PGA version of the Motorola 68010, the Motorola 68012, which did have more address pins, so that 31 bits of address could be provided external to the chip. Guy Harris (talk) 21:23, 23 May 2021 (UTC)